Constant Voltage Biasing of Common Source Amplifier
The NMOS is biased in saturation with and . Now, on applying a small signal input (having a source resistance of ) in series with the bias voltage , the voltage at the gate of the NMOS will be . Also, a load resistance is connected in series with bias voltage such that in the small signal equivalent of the circuit, the other end of will be effectively grounded. Doing that makes the voltage at drain , which is lower than the required bias voltage . So, the bias voltage source is adjusted to a value of
Not so obvious note: In this configuration of CS amplifier, we generally sense the output at the drain terminal of the MOSFET. We have to connect a load like (or other similar loads) instead of directly connecting the drain of the NMOS to the bias voltage (or to ground in small signal model) because, then the drain and source ends of the MOSFET will be essentially fixed at those voltages allowing no swings at all. So, to convert the fluctuations due to the input changes into voltage fluctuations at the output, we pass that through a resistor which according to allows us to sense the voltage across it that changes proportionally with the changing
The problem with the above configuration is we don't generally have biasing voltage sources whose both terminals are available to tap as one of their terminals is often grounded.
In place of the voltage source , we can use a capacitor that is charged to the same bias voltage. We would need a capacitor of infinite capacitance to supply current without dropping in voltage, as there exists a parasitic resistor parallel with the capacitor constantly discharging the capacitor. To tackle this, let's place the voltage source as shown in the circuit below.
If the voltage source is directly connected to the capacitor, then the gate voltage of the MOSFET will be fixed at not allowing it to sense . So let's place a resistor in between and then see the voltage at the gate due to both the sources and .
By applying superposition
with only: the steady state voltage of the capacitor will be equal to (neglecting the minute parasitic resistor). Not so obvious note: Capacitors don't block DC currents, they can go on charging to infinity if connected to a constant DC current source. But, in this configuration that doesn't happen because if the capacitor charges more than volts, then the direction of current will reverse and it will discharge back to and vice-versa.
with only: assuming the capacitor allows the input frequency with no impedance, the voltage at the gate will be
for most of the to appear as
Now, to know the safe value of capacitance that will allow the input frequency unimpeded let's include the capacitance in calculating at a given frequency