Constant current biasing of common source amplifier

As seen in Constant Voltage Biasing of Common Source Amplifier the operating point voltage $V_{D}$ depends according to the equation $V_{D} = V_{D D} - I_{D} R_{L}$ . For the operating point to be stable $I_{D}$ must be stable, but $I_{D} = \frac{1}{2} μ n C_{o x} \frac{W}{L} (V_{G S} - V_{t h})^{2}$ and $μ n C_{o x}$ and $V_{t h}$ vary much with varying temperatures, especially $V_{t h}$ . For a fixed $V_{G S}$ as biased in constant voltage biasing, changing temperatures will affect $I_{D}$ very much. Furthermore as $g_{m} = \sqrt{2 I_{D} μ n C_{o x} \frac{W}{L}}$ , the small signal transconductance will also vary with varying $I_{D}$ . To solve this problem, we shall keep tuning $V_{G S}$ such that $I_{D}$ remains constant and equal to a reference current $I_{r e f}$ under any temperature. This will require a feedback mechanism. Ideally, we can compare the two values and obtain the difference $I_{r e f} - I_{D}$ and if that is $> 0$ (meaning $I_{D}$ is smaller than what's required) we shall adjust $V_{G S}$ by increasing it to increase $I_{D}$ until $I_{r e f} - I_{D} = 0$ .

This mathematical subtraction is implemented in a circuit by connecting a current source $I_{r e f}$ to the drain. The current flowing out of the node is the difference between $I_{r e f}$ and $I_{D}$ . This difference current flows into the parasitic capacitance at the node $x$ . If the difference is positive ( $I_{F} > I_{D}$ ), the voltage across the capacitor ( $V_{x}$ ) increases.

Since the corrective action requires increasing the gate voltage $V_{G}$ , and the drain voltage $V_{x}$ is already increasing, the drain can be shorted to the gate. This configuration, where the gate and drain are shorted, is referred to as a diode-connected transistor. This connection provides negative feedback that automatically adjusts $V_{G S}$ to sustain the reference current.

In this configuration, $V_{G S} = V_{D S}$ . Since $V_{D S} = V_{G S} > V_{G S} - V_{T H}$ , the transistor operates in the saturation region. The feedback automatically sets the gate voltage to:

V_{G S} = V_{T H} + \sqrt{\frac{2 I_{r e f}}{μ_{n} C_{o x} (W / L)}}

If $V_{T H}$ increases due to temperature, $V_{G}$ will essentially increase by the same amount to keep the quantity $(V_{G S} - V_{T H})$ and the current $I_{D}$ constant.

Current Mirrors and Scaling

Let's use the notation $V_{G S} (M 1, I_{r e f})$ to represent the gate voltage required for transistor M1 to conduct $I_{r e f}$ , this voltage can be used to bias other transistors. If this voltage is applied to the gate of a second, identical transistor (M2), and assuming both transistors have identical parameters ( $μ_{n} C_{o x}$ , $W$ , $L$ , $V_{T H}$ ) due to close proximity on the chip, M2 will carry the same current $I_{0}$ . This structure is called a current mirror.

To scale currents, transistor widths are scaled. Placing two identical transistors in parallel to obtain $2 \times I_{0}$ is equivalent to using a single transistor with double the width ( $2 W$ ). Therefore, scaling widths is the fundamental method for scaling currents. Scaling lengths is not recommended.

Small Signal Analysis of the Biased Circuit

We shall tap the $V_{G}$ of the diode connect MOSFET and use that in place of $V_{A}$ , so that the bias voltage will adjust itself to keep $I_{D}$ constant as shown in the circuit. We will do small-signal analysis for this modified circuit and see if our biasing works as expected.

In small-signal analysis, capacitors behave as short circuits, and DC current sources behave as open circuits.

The diode-connected transistor (M1) has its gate and drain shorted, effectively becoming a two-terminal (one-port) network. For small signals, this nonlinear one-port network acts as a resistance of value $1 / g_{m 1}$ . In essence, the current through the diode connected MOSFET in the small signal model (or any MOSFET under saturation) is $i_{d} = g_{m} v_{g s}$ , in this case $v_{g s} = v_{d s}$ i.e., $i_{d} = g_{m} v_{d s}$ a device through which the current is proportional to voltage across it is a resistor. In this case the resistance equals $\frac{1}{g_{m_{1}}}$

The small-signal gate voltage at the amplifier ( $v_{g 2}$ ) is determined by the voltage divider formed by the source resistance $R_{S}$ , the bias resistor $R_{B}$ , and the equivalent resistance of the diode-connected transistor $1 / g_{m 1}$ :

v_{g 2} = v_{i n} \frac{R_{B} + 1 / g_{m 1}}{R_{S} + R_{B} + 1 / g_{m 1}}

Ideally, this fraction should be close to 1. Without $R_{B}$ , the expression would involve only $1 / g_{m 1}$ and $R_{S}$ . Since $g_{m}$ is typically large for high gain, $1 / g_{m 1}$ is small, which would result in significant signal attenuation. The series resistor $R_{B}$ ensures the fraction remains close to 1.

The small-signal output voltage is given by:

v_{o u t} = - g_{m 2} (R_{L} | | R_{D}) v_{i n}

This confirms the biasing network operates as expected without disrupting the small-signal amplification.

Alternative Topology: Source Feedback

Constant-current biasing relies on sensing the drain current and adjusting $V_{G S}$ . This sensing can occur at the drain or the source, and the adjustment can apply to the gate or the source, resulting in four possible combinations. The diode-connected transistor senses at the drain and adjusts the gate.

An alternative method involves sensing the current at the source and adjusting the source voltage. In this topology, the gate voltage is held constant. The reference current $I_{r e f}$ is connected to the source. The circuit compares the drain current $I_{D}$ with $I_{r e f}$ at the source node.

If $I_{D} - I_{r e f} > 0$ , the net positive current flows into the parasitic capacitance at the source, causing the source voltage to increase. As the source voltage increases (with a fixed gate voltage), $V_{G S}$ decreases. A decrease in $V_{G S}$ causes $I_{D}$ to decrease, correcting the error.

The source voltage $V_{S}$ automatically adjusts to:

V_{S} = V_{B} - V_{G S (@ I_{r e f})}

where $V_{B}$ is the fixed gate voltage and $V_{G S} (I_{r e f})$ is the gate-to-source voltage required to sustain the reference current.

For small signals, the source terminal must be an incremental ground. While an ideal voltage source equal to the bias voltage would achieve this without disrupting the DC operating point, voltage sources are not practical on-chip. Instead, a large capacitor ( $C_{3}$ ) is placed at the source. In steady state, no DC current flows through the capacitor, so the drain current equals $I_{0}$ , and the capacitor charges to the required source bias voltage. Ideally, $C_{3}$ acts as a short circuit for small signals. Gate voltage $V_{D}$ is biased using a resistive divider as in the earlier case and the load resistor $R_{L}$ is coupled with $C_{2}$ (everything remains same except that a current source and a capacitor $C_{3}$ is added at the source as shown in the circuit diagram)

Capacitor Sizing ( $C_{3}$ )

To determine the size of capacitor $C_{3}$ , one must find the equivalent resistance seen by the capacitor ( $R_{e q}$ ) and ensure the capacitor's impedance is much smaller than $R_{e q}$ .

To find $R_{e q}$ :

Open DC current sources and short DC voltage supplies ( $V_{D D}$ ) to ground.
Assume other coupling capacitors are shorted.
Remove $C_{3}$ and apply a test voltage $V_{t e s t}$ .
Set the independent small-signal input $V_{i n}$ to zero.

With $V_{i n} = 0$ , the small-signal gate voltage $V_{g}$ is zero. The transistor model includes a dependent current source $g_{m} V_{g s}$ . Since the gate is grounded and the source is at $V_{t e s t}$ , $V_{g s} = 0 - V_{t e s t} = - V_{t e s t}$ . The current flowing downward is $- g_{m} V_{t e s t}$ . Therefore, the current flowing upward (supplied by the test source) is $+ g_{m} V_{t e s t}$ .

The effective resistance is:

R_{e q} = \frac{V_{t e s t}}{I_{t e s t}} = \frac{V_{t e s t}}{g_{m} V_{t e s t}} = \frac{1}{g_{m}}

Note: The capacitor $C_{3}$ is sized such that it is effectively shorted to ground in the small signal model. For that to occur the resistance in series with $C_{3}$ and the $V_{t e s t}$ should be high in comparison with $\frac{1}{ω C_{3}}$ i.e.,

\frac{1}{ω C_{3}} ≪ \frac{1}{g_{m}}

PMOS Common-Source Amplifier

For a PMOS transistor to operate in saturation, the source-to-gate voltage ( $V_{S G}$ ) must exceed the modulus of the threshold voltage ( $| V_{T H} |$ ), and the source-to-drain voltage ( $V_{S D}$ ) must exceed $V_{S G} - | V_{T H} |$ . This condition implies:

V_{S} - V_{D} > V_{S} - V_{G} - | V_{T H} |

V_{D} < V_{G} + | V_{T H} |

In contrast, an NMOS transistor requires $V_{D} > V_{G} - V_{T H}$ . For NMOS, a higher drain voltage relative to the gate aids saturation; for PMOS, a lower drain voltage relative to the gate is better.

With respect to small-signal behavior, NMOS and PMOS transistors are identical and share the same equivalent circuit. For a PMOS common-source amplifier, the source is the small-signal ground, and the input is applied to the gate.

Biasing the PMOS Amplifier:

Since current flows from source to drain in a PMOS device, the source is connected to the highest potential, $V_{D D}$ . Ideally, an ideal voltage source would be used, but practically, the source is connected to $V_{D D}$ . The drain connects to a resistor $R_{D}$ and the load $R_{L}$ .

If the input voltage is connected directly to the gate without a DC shift, the DC gate voltage is zero. While this satisfies the saturation condition $V_{S G} = V_{D D} > | V_{T H} |$ (providing maximum drive), it may violate the condition $V_{D} < V_{G} + | V_{T H} |$ . If $V_{G} = 0$ , the drain voltage must be less than $| V_{T H} |$ (e.g., 0.4 V). While possible, it is often better to add a DC shift to the gate to ensure the gate potential is higher than the drain potential, keeping the transistor in saturation.

The complete circuit uses a capacitor to couple the input and a resistor (or resistive divider) to set the DC bias at the gate. Constant-current biasing for PMOS follows the same logic as NMOS: compare the current with a reference and adjust the gate or source voltage.